A cache memory is a well known instrument for bridging the gap between processor speed and main memory speed. Copies of data from main memory are kept in a cache memory, so that to access such copies the processor needs to access only the fast cache memory and not the slow main memory.
U.S. Pat. No. 5,649,144 provides for a cache management unit that prefetches copies of data into the cache before this data is actually read by the processor. The cache management unit makes use of the concept of address streams and prefetches data from the addresses in the streams, either individually or as part of a prefetched block of data. Each stream is described for example by a base address and a stride value, which define a series of addresses obtainable by starting with the base address and incrementing it repeatedly with the stride value. Both the base address and the stride are adjustable; the stride may take values like plus or minus one or plus or minus a larger value.
The idea behind using address streams is that a typical program executed by the processor will contain instructions that read from the addresses defined by the streams. Once data has been accessed at one address from a stream, it may be expected that in the near future the program will need to access data at a new address obtained by adding the stride value to that one address, possibly after reading from other addresses not belonging to the stream. To anticipate the need for data from new addresses the cache management unit prefetches the data from the new address into the cache memory, so that the processor can quickly fetch the data stored at the new address when it is needed.
Between reading one address and the new address from the stream the processor may read from different addresses, which may be part of different streams or unrelated to any stream. The cache management unit keeps track of progress of the execution of the program by the processor and prefetches data from a particular stream each time when the program executed by the processor has advanced so far that it is expected to a new address from the particular stream at short notice.
The cache management unit must also select cache locations for storing any data needed by the processor, which includes both data stored at addresses belonging to the streams and other data. The cache uses a replacement strategy to select cache locations that it makes available for reuse. One popular replacement strategy, for example, is the LRU strategy (Least Recently Used), which selects the cache memory location occupied by the least recently used data item (or block of data).
If a particular cache memory location is made available for reuse then the data previously stored at that particular cache memory location can only be fetched from slow memory. Therefore, the replacement strategy will have an effect on the efficiency of execution of the program and the use of the bus which connects the process or to main memory. The LRU strategy for example may also reduce the efficiency of the processor and bus use in this way.
Amongst others, it is an object of the invention to provide for a data processing circuit according to the preamble in which the processor can use the cache memory more efficiently.